1. Field of the Invention
The present invention relates to a digital-analog conversion circuit and its output data correction method and, particularly, to a digital-analog conversion circuit including a correction unit that makes correction to digital input data.
2. Description of Related Art
In recent electronic equipment, conversion of digital data into an analog signal is widely used to control various kinds of equipment based on digital data obtained as a result of performing digital processing. A digital-analog conversion circuit (DAC) is a circuit that converts digital data into an analog signal. FIG. 7 shows an example of the digital-analog conversion circuit.
A digital-analog conversion circuit 100 shown in FIG. 7 is a cyclic digital-analog conversion circuit, which is an example of the digital-analog conversion circuit. The cyclic digital-analog conversion circuit 100 includes an amplifier AMP, capacitors C1 to C3, and a plurality of switches. When a digital input signal b(n) is High level (b(n)=1), the switch S1 is ON, and digital input data Vref is input to the digital-analog conversion circuit 100. On the other hand, when the digital input signal b(n) is Low level (b(n)=0), the switch S2 is ON, and input of the digital-analog conversion circuit 100 is connected to the ground. The capacitor C1 receives digital input data Vref*b(n) through a switch and is connected to the amplifier AMP through another switch. The capacitor C2 is connected between the input terminal and the output terminal of the amplifier AMP. The capacitor C3 is connected in parallel with the capacitor C2. Switches are connected at both ends of the capacitor C3, so that the capacitor C3 can be disconnected from the capacitor C2.
The cyclic digital-analog conversion circuit 100 receives digital input data as serial data. Then, the cyclic digital-analog conversion circuit 100 repeatedly performs sampling operation that samples the received data and integral operation of the sampled value with use of the circuit shown in FIG. 7, and thereby outputs an analog signal. The cyclic digital-analog conversion circuit 100 switches between the sampling operation and the integral operation according to control clocks φ1 and φ2. FIG. 8 shows a timing chart of the control clocks. As shown in FIG. 8, the control clocks φ1 and φ2 are generated based on an operating clock, and the control clock φ1 is High level in the first half period of one conversion period and the control clock φ2 is High level in the latter half period of the conversion period. The switch denoted by the symbol φ1 in FIG. 7 has continuity during the High level period of the control clock φ1, and the cyclic digital-analog conversion circuit 100 is in the sampling mode to perform the sampling operation. The switch denoted by the symbol φ2 in FIG. 7 has continuity during the High level period of the control clock φ2, and the cyclic digital-analog conversion circuit 100 is in the integral mode to perform the integral operation.
FIG. 9A is a circuit diagram of the cyclic digital-analog conversion circuit 100 in the sampling mode, and FIG. 9B shows is a circuit diagram of the cyclic digital-analog conversion circuit 100 in the integral mode. The operation of the cyclic digital-analog conversion circuit 100 is described hereinafter with reference to FIGS. 9A and 9B.
Referring to FIG. 9A, the capacitor C1 in the sampling mode is connected between an input terminal and a virtual ground point (e.g. a ground terminal). Further, in the sampling mode, the capacitor C1 is disconnected from the amplifier AMP. The capacitor C2 is connected between the inverting terminal and the output terminal of the amplifier AMP. The capacitor C3 is disconnected from the capacitor C2, and both terminals of the capacitor C3 are connected to the virtual ground point (e.g. a ground terminal). The charge capacitance of each capacitor on the basis of the virtual ground point in the sampling mode is as follows. Specifically, if the charge capacitance of the capacitor C1 is Q1a, the charge capacitance of the capacitor C2 is Q2a and the charge capacitance of the capacitor C3 is Q3a, the charge capacitances Q1a to Q3a are represented by the following expressions (1) to (3). In the expressions (1) to (3), n indicates an operating period number.Q1a=C1×(−Vref×b(n))  (1)Q2a=C2×(−Vout(n−1))  (2)Q3a=0  (3)
Referring then to FIG. 9B, the capacitor C1 in the integral mode is disconnected from the input terminal. The capacitor C1 is connected between the virtual ground point (e.g. a ground terminal) and the inverting terminal of the amplifier AMP. The capacitor C2 is connected between the inverting terminal and the output terminal of the amplifier AMP. The capacitor C3 is connected in parallel with the capacitor C2. The charge capacitance of each capacitor on the basis of the virtual ground point in the integral mode is as follows. Specifically, if the charge capacitance of the capacitor C1 is Q1b, the charge capacitance of the capacitor C2 is Q2b and the charge capacitance of the capacitor C3 is Q3b, the charge capacitances Q1b to Q3b are represented by the following expressions (4) to (6). In the expressions (4) to (6), n indicates an operating period number.Q1b=0  (4)Q2b=C2×(−Vout(n))  (5)Q3b=C3×(−Vout(n))  (6)
The cyclic digital-analog conversion circuit 100 performs conversion operation by switching between the sampling mode and the integral mode at given intervals. The charge capacitance of each capacitor on the basis of the virtual ground point is equal in the sampling mode and in the integral mode. Therefore, the following expression (7) can be derived from the expressions (1) to (6).−C1×(Vref×b(n))−C2×Vout(n−1)+0=0−C2×Vout(n)−C3×Vout(n)  (7)
If an output analog value Vout(n) is calculated from the expression (7), the analog value Vout(n) is represented by the following expression (8).
                              Vout          ⁡                      (            n            )                          =                                                            C                ⁢                                                                  ⁢                2                                                              C                  ⁢                                                                          ⁢                  2                                +                                  C                  ⁢                                                                          ⁢                  3                                                      ×                          Vout              ⁡                              (                                  n                  -                  1                                )                                              +                                                    C                ⁢                                                                  ⁢                1                                                              C                  ⁢                                                                          ⁢                  2                                +                                  C                  ⁢                                                                          ⁢                  3                                                      ×                          (                              Vref                ×                                                                  ⁢                                  b                  ⁡                                      (                    n                    )                                                              )                                                          (        8        )            
The expression (8) shows that the analog value Vout(n) that is output from the cyclic digital-analog conversion circuit 100 is determined by the capacitance ratio of the capacitors C1 to C3. In the cyclic digital-analog conversion circuit 100, the sampling mode and the integral mode correspond to one operating period, and the conversion operation of multi-bit digital input signal b(n) is performed by repeating the period. An analog value Vout(10) when the number of repetition n is 10 (i.e. the number of bits of the digital input signal b(n) is 10) and the capacitances of the capacitors C1 to C3 are the same is represented by the following expression (9).
                              Vout          ⁡                      (            10            )                          =                                                            (                                  1                  2                                )                            1                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    10                    )                                                              )                                +                                                    (                                  1                  2                                )                            2                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    9                    )                                                              )                                +                                                    (                                  1                  2                                )                            3                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    8                    )                                                              )                                +                                                    (                                  1                  2                                )                            4                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    7                    )                                                              )                                +                                                    (                                  1                  2                                )                            5                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    6                    )                                                              )                                +                                                    (                                  1                  2                                )                            6                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    5                    )                                                              )                                +                                                    (                                  1                  2                                )                            7                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    4                    )                                                              )                                +                                                    (                                  1                  2                                )                            8                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    3                    )                                                              )                                +                                                    (                                  1                  2                                )                            9                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    2                    )                                                              )                                +                                                    (                                  1                  2                                )                            10                        ×                          (                              Vref                ×                                  b                  ⁡                                      (                    1                    )                                                              )                                                          (        9        )            
The expression (9) shows that the cyclic digital-analog conversion circuit 100 can convert multi-bit digital input data according to the number of repetition.
As described above, in the cyclic digital-analog conversion circuit 100, an output result is affected by relative variation in the capacitances of the capacitors C1 to C3. Thus, an analog value Vout(n) when an ideal capacitance of the capacitors C1 to C3 is Cunit and the respective variations of the capacitors C1 to C3 are ΔC1 to ΔC3 is represented by the following expression (10).
                              Vout          ⁡                      (            n            )                          =                                                                              C                  ⁢                                                                          ⁢                  unit                                ⁢                                                                  +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  2                                                                              2                  ⁢                  C                  ⁢                                                                          ⁢                  unit                                +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  2                                +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  3                                                      ×                          Vout              ⁡                              (                                  n                  -                  1                                )                                              +                                                                      C                  ⁢                                                                          ⁢                  unit                                +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  1                                                                              2                  ⁢                  C                  ⁢                                                                          ⁢                  unit                                ⁢                                                                  +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  2                                +                                  Δ                  ⁢                                                                          ⁢                  C                  ⁢                                                                          ⁢                  3                                                      ×                          (                              Vref                ×                                                                  ⁢                                  b                  ⁡                                      (                    n                    )                                                              )                                                          (        10        )            
In the expression (10), if the variations ΔC1 to ΔC3 of the capacitors C1 to C3 have a different amount of variations, it is difficult to maintain the linearity between the first term and the second term of the expression (10), which causes degradation of the linearity of an output result. A technique for improving the linearity of an output result in a cyclic digital-analog conversion circuit is disclosed in Japanese Unexamined Patent Application Publications Nos. 63-42523 and 2007-235379, for example.
In an error detection and correction method of a cyclic digital-analog conversion circuit disclosed in Japanese Unexamined Patent Application Publication No. 63-42523, input data composed of two-valued binary code is converted into two multi-valued binary codes indicating the same value. Then, a difference in a result of digital-analog conversion on the respective input data or DNL (Differential Non-Linearity) characteristics is measured. Further, a capacitance error amount of the capacitor in the circuit is calculated, and the capacitance of the capacitor is tuned. The DNL characteristics are thereby improved in the cyclic digital-analog conversion circuit disclosed in Japanese Unexamined Patent Application Publication No. 63-42523.
In the technique disclosed in Japanese Unexamined Patent Application Publication No. 2007-235379, a capacitor is added to a cyclic digital-analog conversion circuit. Then, a switching method for the capacitor is altered, so that the capacitor to be used for charging is changed for each input bit. A plurality of capacitors are thereby used evenly in the cyclic digital-analog conversion circuit disclosed in Japanese Unexamined Patent Application Publication No. 2007-235379, thus dispersing the effect of the relative variation in the capacitances of the capacitors among bits. The effect of the relative variation in the capacitances of the capacitors is thereby reduced in the cyclic digital-analog conversion circuit disclosed in Japanese Unexamined Patent Application Publication No. 2007-235379.